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3000-pixel ccd linear image sensor (b/w) description the ILX103A is a rectangular reduction type ccd linear image sensor designed for bar code pos hand scanner and optical measuring equipment use. a built-in timing generator and clock-drivers ensure single 5v power supply for easy use. features number of effective pixels: 3000 pixels pixel size: 7m 200m (7m pitch) s/h output built-in timing generator and clock-drivers output amplifier gain switching function (2-level: switching gain ratio 1:4) sip small package clock frequency: 500khz (typ.), 100khz (min.), 1mhz (max.) absolute maximum ratings supply voltage v dd 6v operating temperature ?0 to +60 ? storage temperature ?0 to +80 ? pin configuration (top view) internal structure ?1 e98x48a91-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. ILX103A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 v dd gnd vout vgg f clk swg nc nc f rog f shut gnd v dd t1 v dd gnd nc 3000 vgg gnd v dd v dd gnd v dd gnd d24 d25 d54 d55 s1 s2 s3 s2999 s3000 d56 d65 output amplifier driver readout gate readout gate ccd analog shift register ccd analog shift register driver readout gate pulse generator shutter pulse generator timing generator 4 2 1 12 11 14 15 6 13 5 9 10 f shut f rog f clk t1 swg vout 3 16 pin sip (ceramic)
? 2 ILX103A pin description pin no. symbol description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd gnd vout vgg f clk swg nc nc f rog f shut gnd v dd t1 v dd gnd nc power supply gnd signal output output circuit gate bias clock pulse input control (output circuit amplification factor 4/ 1) nc nc readout gate pulse input electrical shutter pulse input gnd power supply test (connect to gnd with 1000pf capacitor) power supply gnd nc recommended voltage item v dd min. 4.5 mode description output circuit gain high low pin 6 swg v dd gnd typ. 5.0 max. 5.5 unit v input pin capacity symbol c f clk c f rog c f shut min. typ. 10 10 10 max. unit pf pf pf item input capacity of f clk pin input capacity of f rog pin input capacity of f shut pin
? 3 ILX103A electro-optical characteristics (analog characteristic) (note 1) ta = 25 c, v dd = 5v, clock frequency: 500khz, light source = 3200k, ir cut filter: cm-500s (t = 1.0mm), output circuit gain low mode item symbol min. typ. max. unit remarks sensitivity 1 sensitivity 2 sensitivity nonuniformity saturation output voltage dark voltage average dark signal nonuniformity image lag dynamic range saturation exposure 5v current consumption total transfer efficiency output impedance offset level r1 r2 prnu v sat v drk dsnu il dr se i vdd tte z o v os 52.5 0.6 92.0 75 925 5.0 0.8 2.5 5.0 5.0 320 0.01 7.0 97.0 250 2.5 97.5 10.0 6.0 12.0 17.0 v/(lx ?s) v/(lx ?s) % v mv mv % lx ?s ma % v note 2 note 3 note 4 note 5 note 6 note 7 note 8 note 9 note 10 note) 1. in accordance with the given electro-optical characteristics, the even black level is defined as the average value of d24, d25 to d53. 2. for the sensitivity test light is applied with a uniform intensity of illumination. 3. light source: led l = 660nm 4. prnu is defined as indicated below. ray incidence conditions are the same as for note 2. prnu = 100 [%] the maximum output of the effective pixels is set to v max , the minimum output to v min and the average output to v ave . 5. integration time is 10ms. 6. the difference between the maximum and average values and the difference between the minimum and average values of the dark output voltage is calculated. the larger value is defined as dark signal nonuniformity. integration time is 10ms. 7. typical value is used for clock pulse and readout pulse. v out = 500mv. 8. dr = v sat /v drk when optical integration time is shorter, the dynamic range sets wider because dark output voltage is in proportion to optical integration time. 9. se = v sat /r1 10. vos is defined as indicated below. (v max ?v min )/2 v ave d 5 1 d 5 2 v o u t v o s g n d d 5 3 d 5 4 d 5 5 s 1
? 4 ILX103A 1 d 1 d 0 5 0 5 0 5 f r o g f s h u t f c l k v o u t o p t i c a l b l a c k ( 3 0 p i x e l s ) d u m m y s i g n a l ( 5 5 p i x e l s ) 1 - l i n e o u t p u t p e r i o d ( 3 0 6 6 p i x e l s ) 3 1 0 0 o r m o r e c l o c k p u l s e s a r e r e q u i r e d . e f f e c t i v e p i c t u r e e l e m e n t s s i g n a l ( 3 0 0 0 p i x e l s ) d u m m y s i g n a l ( 1 0 p i x e l s ) 0 d 2 d 3 d 4 d 2 1 d 2 2 d 2 3 d 2 4 0 1 2 d 5 3 d 5 4 d 5 5 s 1 s 2 s 3 s 4 s 2 9 9 8 s 2 9 9 7 s 2 9 9 9 s 3 0 0 0 d 5 6 d 5 7 d 5 8 d 5 9 d 6 1 d 6 0 d 6 2 d 6 3 d 6 4 d 6 5 clock timing diagram
? 5 ILX103A input clock voltage condition min. 3.0 0.0 typ. v dd max. 5.5 0.1 unit v v item v ih v il symbol t 1, t 2 min. 0 40 typ. 10 50 max. 100 60 unit ns % item f clk pulse rise/fall time f clk pulse duty * 1 symbol t 5 t 9 t 6, t 8 t 7 min. 1/8 t 1/8 t 0 6 t typ. 1/4 t 1/4 t 10 10 t max. 3/8 t 3/8 t 100 20 t unit ns ns ns ns item f rog, f clk pulse timing 1 f rog, f clk pulse timing 2 f rog pulse rise/fall time f rog pulse period * this is applied to the all external pulses. ( f clk, f rog, f shut) f clk timing (for all modes) t 1 t 3 t 4 t 2 f c l k * 1 100 t 4/ ( t 3 + t 4) f rog, f clk timing t 6 t 7 t 8 f r o g f c l k t 9 t 5 note) t is the period of f clk.
? 6 ILX103A f shut, f clk timing symbol t 11, t 13 t 12 t 14 t 15 min. 0 4000 150 150 typ. 10 5000 200 200 max. 100 250 250 unit ns ns ns ns item f shut pulse rise/fall time f shut pulse period f shut, f clk pulse timing 1 f shut, f clk pulse timing 2 f s h u t f c l k t 1 1 t 1 2 t 1 3 t 1 5 t 1 4 symbol t 16 min. typ. 230 max. unit ns item f clk-vout output delay time1 f c l k v o u t t 1 6 * 2 * 1 fck = 500khz, f clk duty = 50%, f clk rise/fall time = 10ns * 2 is data period. f clk output signal timing * 1 note) the high periods of f rog and f shut are separated for 10 t or more.
? 7 ILX103A application circuit (output gain low mode) * 1 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 v d d 3 k 1 / 1 6 v 0 . 0 1 1 0 0 0 p 2 2 / 1 0 v f c l k f r o g f s h u t 5 v 2 s a 1 1 7 5 s i g n a l o u t p u t g n d v o u t v g g f c l k s w g n c n c f r o g f s h u t g n d v d d t 1 v d d g n d n c * 2 * 1 this circuit diagram is the case when output circuit gain is low. * 2 connect t1 (pin 13) to gnd with 1000pf capacitor. application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 8 ILX103A example of representative characteristics (v dd = 5v, ta = 25 c) 1 0 9 8 7 6 5 4 3 2 1 0 4 0 0 5 0 0 6 0 0 7 0 0 w a v e l e n g t h [ n m ] s p e c t r a l s e n s i t i v i t y c h a r a c t e r i s t i c s ( s t a n d a r d c h a r a c t e r i s t i c s ) r e l a t i v e s e n s i t i v i t y 8 0 0 9 0 0 1 0 0 0 1 0 5 1 0 . 5 0 . 1 0 . 0 5 0 . 0 1 1 0 0 1 0 2 0 t a a m b i e n t t e m p e r a t u r e [ c ] o u t p u t v o l t a g e v s . t e m p e r a t u r e c h a r a c t e r i s t i c s ( s t a n d a r d c h a r a c t e r i s t i c s ) o u t p u t v o l t a g e r a t e 3 0 4 0 5 0 6 0
? 9 ILX103A 5 4 3 2 1 0 1 0 0 1 0 2 0 t a a m b i e n t t e m p e r a t u r e [ c ] o f f s e t l e v e l v s . t e m p e r a t u r e c h a r a c t e r i s t i c s ( s t a n d a r d c h a r a c t e r i s t i c s ) v o s o f f s e t l e v e l [ v ] 3 0 4 0 5 0 6 0 ? v o s ? t a ~ 2 . 1 m v / c 5 4 3 2 1 0 4 . 5 v d d [ v ] o f f s e t l e v e l v s . v d d c h a r a c t e r i s t i c s ( s t a n d a r d c h a r a c t e r i s t i c s ) v o s o f f s e t l e v e l [ v ] 5 5 . 5 ? v o s ? v d d ~ 0 . 4 9 t a = 2 5 c 1 4 1 0 1 2 8 6 4 2 0 4 . 5 5 v d d [ v ] s u p p l y c u r r e n t v s . v d d c h a r a c t e r i s t i c s ( s t a n d a r d c h a r a c t e r i s t i c s ) i v d d s u p p l y c u r r e n t [ m a ] 5 . 5 t a = 2 5 c 1 0 5 1 1 0 t i n t e g r a t i o n t i m e [ m s ] o u t p u t v o l t a g e v s . i n t e g r a t i o n t i m e ( s t a n d a r d c h a r a c t e r i s t i c s ) o u t p u t v o l t a g e r a t e 5 0 1 0 0
? 10 ILX103A notes of handling 1) static charge prevention ccd image sensors are easily damaged by static discharge. before handling be sure to take the following protective measures. a) either handle bare handed or use non-chargeable gloves, clothes or material. also use conductive shoes. b) when handling directly use an earth band. c) install a conductive mat on the floor or working table to prevent the generation of static electricity. d) ionized air is recommended for discharge when handling ccd image sensor. e) for the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) notes on handling ccd cer-sip packages the following points should be observed when handling and installing cer-sip packages. a) remain within the following limits when applying static load to the ceramic portion of the package: (1) compressive strength: 39n/surface (do not apply load more than 0.5mm inside the outer perimeter of the glass portion.) (2) shearing strength: 29n/surface (3) tensile strength: 29n/surface (4) torsional strength: 0.9nm b) in addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) applying repetitive bending stress to the external leads. (2) applying heat to the external leads for an extended period of time with a soldering iron. (3) rapid cooling or heating. (4) applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) prying the upper or lower ceramic layers away at a support point of the low-melting glass. note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) soldering a) make sure the package temperature does not exceed 80 c. b) solder dipping in a mounting furnace causes damage to the glass and other defects. use a grounded 30w soldering iron and solder each pin in less then 2 seconds. for repairs and remount, cool sufficiently. c) to dismount an image sensor, do not use solder suction equipment. when using an electric desoldering tool, ground the controller. for the control system, use a zero cross type. u p p e r c e r a m i c l a y e r 3 9 n l o w e r c e r a m i c l a y e r l o w - m e l t i n g g l a s s ( 1 ) 2 9 n ( 3 ) 0 . 9 n m ( 4 ) 2 9 n ( 2 )
? 11 ILX103A 4) dust and dirt protection a) operate in clean environments. b) do not either touch glass plates by hand or have any object come in contact with glass surfaces. should dirt stick to a glass surface, blow it off with an air blower. (for dirt stuck through static electricity ionized air is recommended.) c) clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. be careful not to scratch the glass. d) keep in a case to protect from dust and dirt. to prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) exposure to high temperatures or humidity will affect the characteristics. accordingly avoid storage or usage in such conditions. 6) ccd image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) normal output signal is not obtained immediately after device switch on.
? 12 ILX103A package outline unit: mm 1 . t h e h e i g h t f r o m t h e b o t t o m t o t h e s e n s o r s u r f a c e i s 1 . 6 0 . 3 m m . 2 . t h e t h i c k n e s s o f t h e c o v e r g l a s s i s 0 . 8 m m , a n d t h e r e f r a c t i v e i n d e x i s 1 . 5 . 1 6 p i n s i p 3 0 . 3 0 . 3 2 1 . 0 ( 7 m 3 0 0 0 p i x e l s ) n o . 1 p i x e l 1 1 6 h v 5 . 0 8 0 . 4 1 . 2 7 4 . 6 5 0 . 8 2 . 2 3 0 . 3 4 . 0 4 . 2 5 . 0 0 . 2 3 . 2 0 . 5 2 . 4 0 . 2 5 1 . 3 2 5 0 . 3 0 . 3 m c e r - s i p t i n p l a t i n g 4 2 a l l o y 1 . 3 g p a c k a g e s t r u c t u r e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s d r a w i n g n u m b e r l s - d 4 ( e )

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